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AR# 22169

10.1 EDK - Using SmartModel, I do not see any bus activity during simulation


I am designing an IP that performs a burst transfer from a FIFO to an external memory (for example, an SDRAM). I can validate my BFM simulation, and now I am trying to simulate the entire system with SmartModel. I have checked my custom peripheral, and it is correct; however, I do not see any bus activity and the "retry" signal goes High frequently.


The startup time of the SDRAM that you are interfacing might be causing this problem. The SDRAM requires 100 ns to initialize. Consequently, during this period, the SDRAM rejects any bus transaction trying to read or write it and issues an opb_retry (non-fatal) error.  


Try running for approximately 200 ns, and you should see some output. You can change the C_SIM_INITTIME_PS parameter to reduce this simulation delay; however, it will always occur in real hardware for the first 100 ns.

AR# 22169
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article