Specify blocks provide a way to annotate timing constraints inside of the Verilog code. Does XST support specify blocks?
No, XST does not support specify blocks. The only methods available for passing timing constraints are through attribute passing and through the UCF.
There is no fix scheduled for this issue.
| AR# 22171 | |
|---|---|
| Date | 12/15/2012 |
| Status | Active |
| Type | General Article |