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AR# 22178

**INTERNAL** LogiCORE Reed Solomon Decoder v5.1 - How do I convert from using the Altera RS Decoder?

Description

Keywords: fec, forward, error, correction

Urgency: Standard

Description:
I have a design which contains the Altera Reed-Solomon Decoder set up in Discrete Mode.
Now, I wish to convert my design to target a Xilinx Device.
Can I use the Xilinx Logicore Reed-Solomon Decoder as a drop in replacement
for the Altera equivalent?

Solution

You will need to be aware of some differences if you wish to use the Xilinx RS Decoder
to perform the same function as the Altera core in Discrete Mode.

Here is a description from the Altera datasheet of Discrete Mode:

A discrete decoder processes one codeword at a time and must be reset
between each codeword. The decoder receives the codeword?s first
symbol on the rising edge of sysclk after reset is de-asserted,
depending on the value of dsin (data is only input when dsin is high).
The dsin signal must remain de-asserted for at least one clock cycle after
reset is de-asserted. The rdyin signal is asserted during reset and
remains asserted until the decoder receives the last codeword symbol.
The outvalid signal is asserted when the decoder outputs valid data on
rsout[]. When dsout is asserted, the discrete decoder outputs one
symbol on each rising clock edge until all data is transferred. The
outvalid signal is de-asserted when all data is transferred. If the
discrete decoder detects more errors than it can correct, it asserts
decfail and presents the uncorrected data on rsout[].


To replicate this behaviour with our core, you would need to use the
asynchronous RESET between codewords.

The functionality of the DSIN pin seems to be the same as our CE pin.
You would also need to pulse SYNC to signal the start of a new codeword.

To emulate the OUTVALID signal, you would need to build this signal
from the BLK_START and BLK_END pulses in our core.

Also, the DECFAIL output seems to be present at the start of the output.
Whereas, with our core, the FAIL output is not asserted until the output
has finished and the BLK_END pulse goes high.

The ERR_CNT signals line up the same in both cores.

The Altera core contains a BYPASS input. This passes the inputs directly to the
outputs without decoding them.
In our core, you can use the DATA_DEL output if you wish to access the un-decoded
data at the output. You could MUX this output with the DATA-OUT output with the select
line controlled by the BYPASS input to gain the same functionality as the Altera core.
The delay on the select line would need to match the latency of the core.


AR# 22178
Date Created 10/06/2005
Last Updated 05/13/2009
Status Archive
Type General Article