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AR# 22199

7.1i EDK sp2 - "plb_gemac_v1_01_a" (PLB_GEMAC) SG DMA transmits invalid data

Description

Urgency: Hot  

 

General Description: 

Why is my "plb_gemac_v1_01_a" operating in SG DMA transmitting invalid data?

Solution

One of the reasons is the Alignment requirement, as described below: 

 

- The Tx Frame Buffer will be Hardware Aligned by Data Realignment Engine (DRE). 

- The Tx Buffer Descriptor is 8-byte aligned, and this is done in Hardware by DRE for SGDMA. However, this function is broken in simple DMA. This will be fixed in the later release of the core. 

- The Rx Frame Buffer should be 8-byte aligned, and the Alignment has to be done by software, 

- The Rx Buffer Descriptor is 8-byte aligned, and the Alignment has to be done by Software Application. 

 

Failure to follow alignment restrictions will result in asserts from the driver or bad/corrupted data being transferred.

AR# 22199
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article