LogiCORE Dual Port Block Memory v6.3 - GUI cannot generate the core with falling clock edge

AR#	22223	Search For Another Answer
Topic	Coregen DP Blk Mem
Last Updated	05/21/2007
Status	Active

Description

Keywords: CORE Generator, generator, ramb, blk, mem, active, negative, xco, parameter

In a Dual Port Block Memory Core v6.3 GUI (page 2), when I select the Port A Active Clock Edge = Falling Edge Triggered, the Rising Edge Triggered is still selected. This option should be mutually exclusive.

Furthermore, when I generate the core with Falling Edge Triggered selected, the resulting core still produces the Rising Edge Triggered Core. This can be verified by opening the generated "xco" file and checking the following line:

CSET port_a_active_clock_edge=Rising_Edge_Triggered

Solution

This is an issue with the Dual Port Block Memory Core GUI; it cannot generate the core with the falling edge triggered clock.

To work around this issue, generate the rising edge triggered clock and invert the clock signal outside the core. This issue will NOT be fixed in the Block Memory Generator Core at this time.