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AR# 22233

LogiCORE PIPE PCI Express - CORE Generator customization GUI incorrectly indicates the maximum payload size (MPS) is 4096 bytes for the Device Capabilities register


General Description:

The customization GUI for the PIPE core in CORE Generator specifies the maximum supported payload size to be 101b or 4096 bytes. The maximum payload size is actually 512 bytes.


The PIPE core's Maximum Payload Size setting should be 512 bytes or less. Valid values for this drop-down field are:

000b - 128 bytes max payload size

001b - 256 bytes max payload size

010b - 512 bytes max payload size

A patch is available at:



Before installing this patch, ensure you have 7.1i Service Pack 3 installed with 7.1i IP Update #3. Further, you should have the PIPE v1.2 core update installed.

To install the patch:

1. Close all Xilinx applications

2. Unzip the contents of the zip file to the root directory of the Xilinx installation

3. Choose to allow the extractor to overwrite all the existing files and maintain the directory structure pre-defined in the archive.

The Xilinx installation directory can be determined by typing "echo %XILINX%" from a command prompt.

4. After installing the patch, regenerate the LogiCORE PCI Express PIPE v1.2 from CORE Generator.

The core and supporting files produced will contain the fixes.

Please close all Xilinx applications before installing this patch. Once installed, reopen CORE Generator and regenerate the PCI Express PIPE core. The device capability MPS field should be customizable up to 512 bytes.

AR# 22233
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article