This patch is applicable to SPI-4.2 Core users that target Virtex-4 only. It does not apply to users that target Virtex-II or Virtex-II Pro. All SPI-4.2 Core users targeting Virtex-4 (v7.3, v7.2, v7.1 and v7.0) must download a patch to address the following three issues:
CR 217100 : (Xilinx Answer 22084) Sink core goes empty when there is 1 packet left in sink FIFO
CR 218335 : (Xilinx Answer 22245) Sink core duplicates data on FIFO interface side
CR 218336 : (Xilinx Answer 22246) Signal SnkFFBurstErr is asserted unexpectedly
If you are currently using SPI-4.2 v7.2, v7.1, or v7.0, you need to upgrade to v7.3 core immediately. The v7.3 core is available with 7.1i IP Update #3. The latest IP Updates are available from the Download Center at:
Once you have installed IP Update #3, you will need to install a patch over your ISE installation.
Follow these steps:
1. Download the patch from:
2. Save the patch in a temporary directory on your system.
3. Using Winzip or other file extraction utility, extract the zip file over your ISE7.1i design tools installation. Typically, on PC systems, this is C:\Xilinx.
4. Generate the SPI-4.2 Core and start your design using the generated files. If you have previously generated SPI-4.2 Core v7.0, v7.1, v7.2 or v7.3, you will need to re-generate the SPI-4.2 Core using the same configuration you have been using. For information on how to generate a core using XCO file, see the Core Generator User Guide.
5. Replace the old sink netlist file (<comp_name>_snk_pl4_top.ngc) with the newly generated netlist file and implement your design from NGDBuild stage. There are no changes to source core netlist or the other files; therefore, there is no need to replace them.
All three issues mentioned in this Answer Record will be fixed in SPI-4.2 v7.4 core, which will be available with ISE8.1i IP Update #1,
tentatively scheduled for January 2006.