UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2224

VERILOG-XL: Error! Module (...) has a `timescale directive but previous modules do not

Description

Keywords: Verilog, Verilog-XL, timescale

Urgency: Standard

General Description:
When simulating with Verilog-XL, what does the following error mean:

Error! Module (...) has a `timescale directive but previous modules do not

Solution

The `timescale compiler directive is optional. Designs that do not
contain this require no modification and the default of 1 ns / 1 ns is used.
However, if the design includes a `timescale compiler directive for any
module definition, then all other modules definitions require this as well.
Otherwise, Verilog-XL flags this as an error.

The `timescale can be declared in any file.

The UNISIMS has 100ps / 10ps.
The SIMPRIMS has 1ps / 1ps.
The glbl.v has 100ps / 10ps.

The smallest precision of all the timescale directives determines the time
unit of the simulation. For example,

`timescale 1 ns / 10 ps
module1 ();
...
endmodule

`timescale 100 ns / 1 ns
module2 ();
...
endmodule

`timescale 1 ps / 100 fs
module3 ();
...
endmodule

The first timescale indicates that the time units for module1 are in multiples
of 1 ns and it is precise to 10 ps. Thus, the smallest timestep for the
simulator is 10 ps.

The second timescale is 100 ns / 1 ns. Since 1 ns is greater than 10 ps,
the smallest timestep remains 10 ps.

The third timescale is 1 ps / 100 fs. Since 100 fs is smaller than 10 ps,
the smallest simulator timestep now becomes 100 fs.


AR# 2224
Date Created 06/03/1997
Last Updated 05/05/2004
Status Archive
Type General Article