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AR# 22259

7.1i EDK - Create/Import Master IP does not perform transactions greater than 0x4 with length register set

Description

Keywords: 7.1, peripheral, IPIF, opb, plb, byte, transaction

Urgency: Standard

General Description:
In EDK, I have generated a custom IP core that is a master on the OPB/PLB bus.

With this core in the USER_LOGIC.vhd, there is a section generated on how to set up the registers to access the PLB/OPB bus. One of them is the Length Register:

-- Length Register (C_BASEADDR + 0x10C):
-- bit 0-15 - Transfer Length (This 16-bit value is used to specify the
-- number of bytes (1 to 65,536) to transfer during user logic
-- master read or write operations)

When I set this register to anything other than 4 bytes (32 bits), the core does not function as expected. If I sent this to 12 bytes for example (3 32 bit words) I would expect to see 3 writes or reads on the PLB/OPB bus, but only 4 bytes get transferred instead of the requested 12 bytes.

Why does this occur?





Solution

This can be rectified by doing the following:

First, in step 6 of the create/import peripheral wizard when generating this core, ensure that you tick the option to "Generate Template driver files to help you implement software interface". This will generate software driver files for your core.

In the <peripheral_name>.h file, the length file id is defined as follows in the constant definitions section:

/**
* User Logic Master Space Offsets
* -- MASTER_CR : user logic master module control register
* -- MASTER_SR : user logic master module status register
* -- MASTER_LA : user logic master module local address (IP2IP_Addr) register
* -- MASTER_RA : user logic master module remote address (IP2Bus_Addr) register
* -- MASTER_LENGTH : user logic master module data transfer length (bytes) register
* -- MASTER_BE : user logic master module byte enable register
* -- MASTER_GO_PORT : user logic master module go bit (to start master operation)
*/
#define MASTER_USER_MASTER_SPACE_OFFSET (0x00000000)
#define MASTER_MASTER_CR_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x00000000)
#define MASTER_MASTER_SR_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x00000001)
#define MASTER_MASTER_LA_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x00000004)
#define MASTER_MASTER_RA_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x00000008)
#define MASTER_MASTER_LENGTH_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x0000000C)
#define MASTER_MASTER_BE_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x0000000E)
#define MASTER_MASTER_GO_PORT_OFFSET (MASTER_USER_MASTER_SPACE_OFFSET + 0x0000000F)

Change the line:

#define MASTER_USER_MASTER_SPACE_OFFSET (0x00000000)

to the following:

#define MASTER_USER_MASTER_SPACE_OFFSET (0x00000100)

Your core should then operate with the required length register setting as expected.
AR# 22259
Date Created 10/26/2005
Last Updated 04/17/2007
Status Archive
Type General Article