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AR# 22277

MIG v2.0 - How can I change the refresh rate?

Description

In the MIG-generated controller design, the refresh rate is set to 7.8 microseconds.

How do I change the refresh rate?

Solution

Starting with the release of MIG 2.1, this information is available in the MIG User Guide.Please see the MIG User Guide for further information.

Changing theRefresh Rate for Virtex-5 DDR and DDR2 Interfaces

Change the top-level parameter, TREFI_NS, to set the selected refresh interval in nanoseconds.

For example, to change the refresh rate to 3.9 microseconds, set TREFI_NS to 3900.

The controller issues a refresh approximately every (TREFI_NS * 1000)/CLK_PERIOD clock cycles, where CLK_PERIOD is the top-level parameter defining the clock period in terms of picoseconds. If the above formula exceeds 4095, you must manually expand the signal refi_cnt_r in the CTRL module beyond 12 bits.

The CKE counter is used for the refresh interval to count down. If you want to change TREFI_NS, you must also modify cke_200us_cnt_r in the ddr2_phy_init hdl file. This ensures that the 200us initialization time is preserved. You need to add or remove bits based on the change you made to the refresh interval.

Changing theRefresh Rate for Virtex-4 DDR2 Interface using the Direct Clocking Read Capture Method and Virtex-4 DDR Interface

Change the global define (for Verilog) or constant (for VHDL) variable max_ref_cnt in the file "mymodule_parameters_0.v" (or .vhd) so that max_ref_cnt = (refresh interval in clock periods) = (refresh interval) / (clock period). For example, for a refresh rate of 3.9 microseconds, for a memory bus running at 200 MHz:

max_ref_cnt = 3.9 microseconds / (clock period) = 3.9 microseconds / 5 ns = 780 (decimal) = 0x30C

If the above value exceeds (2^max_ref_width - 1), the value of max_ref_width must be increased accordingly in the "parameters_0.v/vhd" file to increase the width of the counter used to track the refresh interval.

Changing theRefresh Rate for Virtex-4 DDR2 Interface using the SERDES Read Capture Method

The formula is similar to the Virtex-4 DDR2 Direct Clocking case. However, since the refresh logic in the controller is running at half the memory bus rate, the formula is max_ref_cnt = (refresh interval) / (2 * clock period). For example, for a refresh rate of 3.9us, for a memory bus running at 267 MHz:

max_ref_cnt = 3.9 us / (2 * clock period) = 3.9 us / 7.49 ns = 521 (decimal) = 0x209

If the above value exceeds (2^max_ref_width - 1), the value of max_ref_width must be increased accordingly in the "parameters_0.v/vhd" file to increase the width of the counter used to track the refresh interval.

Changing theRefresh Rate for Spartan-3/-3E Designs

The formula and modification process is the same as for the Virtex-4 DDR and DDR2 Direct Clocking interfaces.

AR# 22277
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
IP
  • MIG