We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22292

8.1i IP Update #1 CORE Generator - IP-DSP What's New and Known Issues List


Keywords: ISE, LogiCORE, Binary Counter, Distributed Arithmetic FIR Filter, FIR Compiler, MAC FIR, MACC FIR, DVB S2 FEC Encoder, FFT, Floating-point, Divider Generator, Pipelined Divider, TCC Decoder 3GPP, CTC Encoder 3GPP

This Answer Record contains the IP-DSP What's New and Known Issues addressed in 8.1i IP Update 1, and contains the following:

- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 22155).



What's New in 8.1i IP Update 1

LogiCORE Binary Counter V8.0
New Features in v8.0 r1:
-- Support added for Virtex-4
-- Support added for ISE 7.1i
-- Area and speed improvements
-- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models
-- New addsub used to optimize bypass and constant count cases

Bug Fixes in v8.0 r1:
-- Maximum output width reduced to 30 bits
-- CR 207668: Core does not generate when data is entered in hex format and a step size of greater than 10 is specified
-- Miscellaneous GUI fixes

LogiCORE Convolutional Encoder v5.0
New Features in v5.0:
-- None

Bug Fixes in v5.0:
-- CR217738: GUI Issue - User-specified codes are not used to generate core (Symptom: Default codes were used for core generation)

LogiCORE Divider Generator v1.0
New Features in v1.0:
-- Nonrestoring Radix-2 algorithm for fixed-point operations
-- Behaves identically to (and supersedes) the Pipelined Divider v3.0 LogiCORE
-- New Repeated Multiplication algorithm for floating-point operations
-- A high-precision algorithm conforms to IEEE 754 format for number representation, including zero, infinity and NaN (Not a Number)
-- Optimally uses advanced primitives (block RAM, Multipliers, and DSP48s) for small, fast implementations
-- Fully pipelined for maximal clock speed and maximal throughput
-- Provides Underflow and Overflow outputs
-- Optional asynchronous and synchronous clear, clock enable

LogiCORE DVB S2 FEC Encoder v1.2
New Features in v1.2:
-- None

Bug Fixes in v1.2:
-- CR 217360: Error in short frame BCH polynomial
-- Spartan-3 data added to Core Performance in Data Sheet

LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1
Features in v3.2:
-- Support added for Spartan-3E
-- "Optimize for Speed using Xtreme DSP Slices" option added to all three architectures. This option in Virtex-4 enables operation of the core at higher clock speeds by using more DSP48s. This provides another way to make trade-offs between resource utilization and performance.
-- "Bit/Digit Reversed Order" or "Natural Order" output available for all three architectures
-- "Input Data Width" and "Phase Factor Width" expanded to include all values from 8 to 24
-- "Run Time Configurable Transform Length" available for all three architectures
-- "Distributed RAM Memory Option" available for Data for Radix-4 Burst I/O as well as Radix-2 Minimum Resources

Bug Fixes in v3.2:
-- CR 199541: Incorrect FFT output results for Radix-4 Burst I/O when using Virtex-4
-- CR 201500: Core will not generate for these two cases:
-- When either the Radix-4 Burst I/O or Radix-2 Minimum Resources architectures are selected and output width = 35 bits with phase factor width = 20 or 24 bits
-- When the Pipelined Streaming I/O architecture is selected and output width > 35 bits with phase factor width = 20 or 24 bits
-- CR 201885: If either Radix-4 Burst I/O or Radix-2 Minimum Resources are selected, the core will not begin processing after the initial triggering of START, unless SCLR is asserted first
-- CR 207964: Maximum clock speed numbers in data sheet v3.1 have been corrected in v3.2
-- CR 209462: VHDL and Verilog Structural Behavioral models give incorrect results

Bug Fixes in v3.2 patch 1:
-- CR 220574: For the Pipelined Streaming I/O architecture, overflow is signaled for frames with no overflow, preceding or following a frame with an overflow (overflow tainting next or previous frame)
-- CR 220203: GUI displays incorrect resource estimates for DSP48 count
-- CR 220655: For the Pipelined Streaming I/O architecture, the core dumps incorrect output data after a reset event (SCLR asserted, or new NFFT value latched in). If two reset events occur less than ~40 CLK cycles apart, the second reset might be incomplete, and the core might start generating output values (DV = 1) from an incomplete input frame.

LogiCORE FIR Compiler v1.0
New Features in v1.0
-- First release
-- Consolidated interface for generation of most FIR filter implementations
-- Incorporates functionality of MAC_FIR_V5_1 and DA_FIR_V9_0 cores

LogiCORE Floating Point v2.0
New Features in v2.0:
-- Support for conversion to and from fixed-point
-- Greater choice of word length
-- User-specifiable latency
-- Level of hardware reuse for divide and square-root can be specified
-- Support for clock enable

Bug Fixes in v2.0:
-- CR 213669: Data sheet does not contain timing information
-- CR 214410: GUI needs to have dynamic format diagram

LogiCORE Multiplier Generator v8.0
New Features in v8.0:
-- Improved support for Spartan-3E embedded multipliers (MULT18X18SIO)
-- New hybrid (One MULT18X18/DSP48 plus fabric) multiplier implementation
-- Redesigned GUI
-- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models

Bug Fixes in v8.0:
-- CR213485: GUI for Multiplier 7.0 has strange behavior
-- CR204167: Multiple generations of Mult. Gen. Core 7.0 results in change of data type
-- CR193082: Multiplier behavioral VHDL does not match back-annotated core for XtremeDSP
-- CR203909: Multiplier core (v7.0) produces an inflexible netlist
-- CR208033: Incorrect latency in Verilog behavioral model
-- CR217341: Multiplier not using registered outputs
-- CR218540: Behavioral simulation shows different latency than expected

LogiCORE TCC Decoder 3GPP v2.0
New Features in v2.0:
-- Support added for Virtex-4
-- Support added for ISE 8.1i
-- Additional pipelining added to increase throughput

Features Removed in v2.0:
-- External interleaver capability removed
-- External block memory capability removed
-- Optional memory management capability removed - memory management unit is always created
-- MAX and MAX STAR algorithm options removed

LogiCORE CTC Encoder 802.16e v1.1
New Features in v1.1
-- First release



LogiCORE Binary Counter V8.0
-- Why do I get the opposite priority of that which I selected for the Load and CE pins in the Binary Counter GUI? See (Xilinx Answer 22295).

LogiCORE Convolutional Encoder v5.0
-- No Known Issues

LogiCORE Divider Generator v1.0
-- No Known Issues

LogiCORE DVB S2 FEC Encoder v1.2
-- No Known Issues

LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1
-- Large FFT point size generation times. See (Xilinx Answer 21988).
-- Some bitwidth fail to allow core to implement. See (Xilinx Answer 20307).

LogiCORE FIR Compiler v1.0
-- How do I convert floating-point coefficients to fixed-point for Xilinx DA and MAC FIR filters? See (Xilinx Answer 5366).
-- How do I determine the latency of my filter? See (Xilinx Answer 22674).
-- Why does the FIR Compiler GUI crash when I enter an invalid Sample Frequency, or leave the Sample Frequency field empty? See (Xilinx Answer 22673).
-- Why does my single-rate or interpolating half-band fully parallel filter fail to generate for Virtex-4? See (Xilinx Answer 22705).
-- Why does my single rate MAC FIR filter fail to generate, giving me an empty or missing netlist and ERROR:sim - NgdBuild:153 or ERROR:NgdBuild:604? See (Xilinx Answer 22706).
-- Why do I receive an Error:sim:57 when trying to generate a MAC FIR? See (Xilinx Answer 22675).
-- Why can I not use the multicolumn support, when my coefficients are symmetrical? See (Xilinx Answer 22936).

LogiCORE Floating Point v2.0

LogiCORE Multiplier Generator v8.0
-- Why does the SCLR not reset the upper bits of a DSP48 based 35 x 18 multiplier? See (Xilinx Answer 23591)
-- Why do I see simulation mismatches between the Verilog Unisim based model, and the back annotated design? See (Xilinx Answer 23597).
-- Why can I not add handshaking signals to my multiplier, when I am targeting a hybrid or constant coefficient multiplier? See (Xilinx Answer 23598).
-- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).
-- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).
-- Why do I see simulation mismatches when using the distributed memory-based constant coefficient multiplier? See (Xilinx Answer 23601).
-- Why are the outputs of my reloadable constant coefficient multiplier incorrect? See (Xilinx Answer 23602).
-- Why are some of the cores that are available in CORE Generator not available for the same device architecture when using Project Navigator to generate the core? See (Xilinx Answer 23603).

LogiCORE TCC Decoder 3GPP v2.0
-- No Known Issues

LogiCORE CTC Encoder 802.16e v1.1
-- No Known Issues



LogiCORE CIC v3.0
-- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).
-- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).
-- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

LogiCORE Complex Multiplier v2.1
-- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

-- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).

LogiCORE Distributed Arithmetic FIR Filter (DA FIR) v9.0
-- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
-- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
-- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

-- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
-- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DCT v2.1
-- DCT can be implemented in Spartan-3 and Virtex-4 devices. See (Xilinx Answer 18937).

LogiCORE DCT v2.1
-- The DCT output width is incorrectly calculated, causing Java errors. See (Xilinx Answer 20459).

LogiCORE DDS v5.0
-- The DDS Data Sheet has an obsolete web link. See (Xilinx Answer 21397).

LogiCORE DDS v5.0
-- The DDS channel output does not operate as expected. See (Xilinx Answer 21474).

LogiCORE 1024-pt FFTv1.0
-- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0
-- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0
-- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0
-- No Verilog model is available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0
-- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

-- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings. See (Xilinx Answer 14861).
-- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE MAC v4.0
-- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).

-- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
-- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).
-- COE Errors reported in wrong format. See (Xilinx Answer 14202).
-- Some bitwidth fail to allow core to implement. See (Xilinx Answer 20307).

LogiCORE Pipelined Divider v3.0
-- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v8.0
-- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).

LogiCORE Reed Solomon Encoder v5.0
-- Information on the Ghost Enable pin in the GUI. See (Xilinx Answer 19526).

LogiCORE Reed Solomon Decoderv5.1
-- Processing delay warning occurs for a 2-Channel Reed Solomon. See (Xilinx Answer 21769).
AR# 22292
Date Created 09/04/2007
Last Updated 03/30/2009
Status Archive
Type General Article