What's New in SPI-4.2 v6.3

- Support for ISE 8.2i

- Support for electronic IP licensing scheme

- Updates for user-configurable Verilog demonstration testbench

Bug Fixes in v6.3

CR 186301: Incorrect behavior in SrcFFOverflow_n and SnkFFOverflow_n signal

CR 183046: Add ASYNC_REG attribute to synchronization logic to prevent "X" propagation during simulation

CR 192231: Change the range of AFAssert and AFNegate to support shallow FIFOs

CR 201429: Idles are not transmitted when the source core goes in frame and there is no data to send

CR 190557: IOSTANDARD for TStat and TSClk in UCF file correction

CR 183354: Add MAXDELAY constraint to reset signals in NCF file

CR 183626: RSClk generation is gated by DcmReset_RDClk instead of Locked _RDClk

CR 187174: Missing TIG constraint for static paths in NCF file

CR 184476: IBUFDS for TStat instantiated incorrectly in wrapper file

CR 194473: Verilog Synthesis Wrapper connection issue

Supported Device and Package Information for SPI4.2 v6.3

SPI4.2 v6.3 Core supports Virtex-II and Virtex-II Pro family. The supported device and package information has not changed from v6.1 Core. Please see information in the following tables.

If you are targeting Virtex-4 family, use the latest SPI-4.2 v8.x series of cores available with IP update.

PL4 v6.3 Virtex-II Device Package Table

PL4 v6.3 Virtex-II Pro Device Package Table

Known Issues SPI4.2 v6.3

Core Generation Issues

(Xilinx Answer 22930) SPI-4.2 v6.3 Core is not visible in CORE Generator

(Xilinx Answer 22931) DataMaxT 1 to 16 is not supported. The core will send training pattern continuously

(Xilinx Answer 15493) When I generate an SPI-4.2 (PL4) Core through CORE Generator, the following errors occur:

......."ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist."

......."ERROR: Did not generate ISE symbol file for core <pl4_core>."

Constraints and Implementation

(Xilinx Answer 22929) Migrating SPI-4.2 Core from v6.2 to v6.3.

(Xilinx Answer 18291) If you are implementing Dual SPI4.2 Core in a single FPGA, consult your local FAE, or contact Xilinx Technical Support.

(Xilinx Answer 18087) SPI-4.2 signals are locked to specific I/O locations. Altering these pin locations is NOT recommended.

(Xilinx Answer 18089) SPI-4.2 signals default to LVDS without the internal device termination. If internal termination is desired, this must be set in the UCF file.

(Xilinx Answer 20527) TStat[1:0], TSClk, RStat[1:0], RSClk defaults to LVDCI_33 I/O Standards if they are not specifically defined.

(Xilinx Answer 18927) When I run an implementation tool with an SPI-4.2 Core, several NGDBuild WARNING and INFO messages are reported.

(Xilinx Answer 18928) Timing Analyzer (TRCE) reports "0 items analyzed".

(Xilinx Answer 23031) Par ERROR: Clock placer is unable to partition the design so that all the clock region constraints are honored.

General Simulation Issues

(Xilinx Answer 16176) Does the SPI-4.2 (PL4) Core have a required startup sequence or reset procedure?

(Xilinx Answer 15579) When I simulate an SPI-4.2 (PL4) Source Core, glitches occur on TDat and TCtl. This is visible on gate-level simulation as well as in timing simulation.

(Xilinx Answer 17686) When I simulate the SPI-4.2 Core, an unknown state or "x" appears on some of the signals.

(Xilinx Answer 18942) (Xilinx Answer 18953) During a simulation, " Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;" occurs.

(Xilinx Answer 15436) Simulation of the SPI-4.2 (PL4) Core using dynamic alignment requires timing simulation to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink Core.

(Xilinx Answer 15578) When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behavior occurs.

(Xilinx Answer 9872) When I run timing simulation in Verilog, there is strange behavior occurring (such as the core never goes in-frame, signals going "x," or pulses are swallowed).

Hardware

(Xilinx Answer 16112) When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.

(Xilinx Answer 15442) An SPI-4.2 (PL4) Sink Core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error.

Other Helpful Answer Records

(Xilinx Answer 18936) What is the power consumption of the v6.2 SPI-4.2 (PL4) Core?

(Xilinx Answer 14968) Is a description of error and control signals available in addition to the information provided in the SPI-4.2 (PL4) Data Sheet?

(Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?

SPI- 4.2 (PL4) v6.2 Known Issues

The PL4 v6.2 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 12420) for information on existing PL4 v6.2 issues.

SPI- 4.2 (PL4) v6.0/6.0.1 Known Issues

The PL4 v6.0/6.0.1 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 18902) for information on existing PL4 v6.0/6.0.1 issues.

SPI-4.2 (PL4) v5.2 Known Issues

The PL4 v5.2 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 17664) for information on existing PL4 v5.2 issues.

SPI-4.2 (PL4) v5.0 Known Issues

The PL4 v5.0 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16546) for information on existing PL4 v5.0 issues.

SPI-4.2 (PL4) v4.0 Known Issues

The PL4 v4.0 Core is now obsolete. Please upgrade to the latest version of the core. See (Xilinx Answer 16331) for information on existing PL4 v4.0 issues.

SPI-4.2 (PL4) v3.x Known Issues

The PL4 v3.x is no longer supported for new customers; please use the latest version of the core. For information on existing PL4 v3.x issues, see (Xilinx Answer 16332).