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AR# 22302

LogiCORE FIFO Generator v2.3 - Release Notes and Known Issues for FIFO Generator Core


General Description:

This Release Note is for the FIFO Generator 2.3 Core released in 8.1i IP Update 1 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 22155).


New Features in v2.3

-Optional reset pin

-Support added for ISE 8.1i

Bug Fixes in v2.3

-CR 221867: Depth reported on summary page was sometimes not reported precisely

-CR 214525: Page 1 of customization GUI is partly cut off visually

Known Issues in v2.3

- (Xilinx Answer 22462) Why are the FIFO16 flags not working correctly?

- (Xilinx Answer 22720) Is the behavioral model supported for FIFO16 FIFO Generator implementations?

- (Xilinx Answer 20278) PROG_EMPTY and PROG_FULL can produce false-assertions

- (Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"

- (Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

- (Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be.

- (Xilinx Answer 22722) Where can I find the User Guide for the FIFO Generator?

AR# 22302
Date Created 12/18/2012
Last Updated 12/20/2013
Status Active
Type General Article