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AR# 22304

LogiCORE Block Memory Generator v1.1 - Release Notes and Known Issues for the Block Memory Generator Core

Description

This Release Note is for the Block Memory Generator Core released in 8.1i IP Update 1, and contains the following information: 

- New Features 

- Bug Fixes 

- Known Issues 

 

For installation instructions and design tools requirements, see (Xilinx Answer 22155)

 

If you would like to migrate the existing Dual-Port Block Memory Core or Single-Port Block Memory Core in your current design with the Block Memory Generator Core, see the migration kit at: 

http://www.xilinx.com/ipcenter/blk_mem_gen/blk_mem_gen_migration_kit.htm

Solution

b>Known Issues in v1.1 

 

General 

 

(Xilinx Answer 22690) The resource count on the last page of the GUI does not match actual block RAM usage  

(Xilinx Answer 22692) 8-bit byte-write will not be supported  

(Xilinx Answer 22790) A Data Sheet error on the behavior of enable pin occurs 

 

CORE Generator Issues 

 

(Xilinx Answer 22693) "ERROR:coreutil - Failure to generate output products"  

(Xilinx Answer 22695) "ERROR:coreutil - Failure to generate output products "COREGen runs out of RAM while generating large memories" 

(Xilinx Answer 22696) Width of the address bus displayed on the symbol is incorrect  

(Xilinx Answer 22697) "Error: Validation Failed when loading COE file"  

 

Core Issues 

 

(Xilinx Answer 22698) "NO_CHANGE" operating mode is not supported when 32kx1 is used  

 

Simulation Issues 

 

(Xilinx Answer 22699) Behavioral models do not flag collisions for asymmetric read-write ports  

(Xilinx Answer 22700) Invalid output occurs when asserting WE and SSR simultaneously in NO_CHANGE mode 

(Xilinx Answer 22701) Output is invalid during a write operation when in "Write First" mode and using byte-write enable  

(Xilinx Answer 22702) The write port output becomes undefined during read-write collision when using NC-Sim

AR# 22304
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article