The Xilinx Distributed Memory Generator v2.1 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE.
See
(Xilinx Answer 21416) for the difference between Distributed Memory Generator and Distributed Memory LogiCOREs.
New Features in v2.1- Initialization of Single and Dual Port Distributed RAMs
- Support for ISE 8.1i
- Added 100 ps delay to sequential assignments in behavioral models
Bug Fixes in v2.1- CR 207921: Incorrect ASY file created for 16-bit-deep SRL16-based memories
- CR 207123: Cannot set base10 default data larger than 32 bit values
- CR 208080: Supported family lists differ between the GUI and the Version Info file
- CR 220873: Default Data is left-aligned instead of right-aligned
-CR 206903: Behavioural modes do not account for situations in which address > depth
Known Issues in v2.1- When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate. See
(Xilinx Answer 21393).