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AR# 22311

LogiCORE Distributed Memory Generator v2.1 - Release Notes and Known Issues for Distributed Memory Generator Core

Description


This Release Note is for the Distributed Memory Generator Core released in 8.1i IP Update 1, and contains the following: 
 
- New Features 
- Bug Fixes 
- Known Issues 
 
For installation instructions and design tools requirements, see (Xilinx Answer 22155).

Solution


The Xilinx Distributed Memory Generator v2.1 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE. 
 
See (Xilinx Answer 21416) for the difference between Distributed Memory Generator and Distributed Memory LogiCOREs. 
 
New Features in v2.1 
 
- Initialization of Single and Dual Port Distributed RAMs 
- Support for ISE 8.1i  
- Added 100 ps delay to sequential assignments in behavioral models  
 
Bug Fixes in v2.1 
 
- CR 207921: Incorrect ASY file created for 16-bit-deep SRL16-based memories  
- CR 207123: Cannot set base10 default data larger than 32 bit values  
- CR 208080: Supported family lists differ between the GUI and the Version Info file  
- CR 220873: Default Data is left-aligned instead of right-aligned  
-CR 206903: Behavioural modes do not account for situations in which address > depth  
 
Known Issues in v2.1 
 
- When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate. See (Xilinx Answer 21393).
AR# 22311
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article