UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22314

MAP, XtremeDSP Slice - Why do I have extra or missing registers in my DSP48, DSP48E, or DSP48A A, B input path that cause my design to fail in timing simulation and hardware when using MAP -timing?

Description

Why do I have extra or missing registers in my DSP48, DSP48E, or DSP48A A, B input path that cause my design to fail in timing simulation and hardware when using the MAP -timing option? The problem usually manifests itself as a design that includes a DSP48 derivative (DSP48, DSP48E, or DSP48A) that works correctly in behavioral simulation, but not in hardware when using the MAP -timing option.

This can affect Spartan-3A DSP (DSP48A), Virtex-4 (DSP48) or Virtex-5 (DSP48E). In the case of Virtex-5, the MAP -timing option is always used and cannot be turned off.

Solution

This is a known problem that has been found on various designs from ISE 7.1i and IDS 10.1.03.

The problem occurs because MAP is attempting to optimize the design by pulling registers out of or into the DSP48 slices. However, in some cases, it is adding registers to the DSP48 slice inputs. This added latency breaks the synchronization and causes problems in hardware and post-PAR simulation, which causes a mismatch with behavioral simulation.

The first recommendation by which to work around this problem is to try the latest release of the Xilinx ISE Implementation tools, as this issue might be fixed in the latest release.

Second, if it is not resolved in the latest release of the ISE Implementation tools, you can work around this problem by setting the following environment variable on your system:

XIL_MAP_NO_DSP_AUTOREG = 1

For information on setting environment variables, see (Xilinx Answer 11630).

If the environment variable does fix your design, please open a case with Xilinx Technical Support so that this issue can be addressed:

http://www.xilinx.com/support/mysupport.htm

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
29120 LogiCORE IP Divider Generator - Release Notes and Known Issues N/A N/A
AR# 22314
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Spartan-3A DSP
  • Less
Tools
  • ISE - 8.1i
  • ISE - 8.1i sp1
  • ISE - 8.1i sp2
  • More
  • ISE - 8.1i sp3
  • ISE - 8.2i
  • ISE - 8.2i sp1
  • ISE - 8.2i sp2
  • ISE - 8.2i sp3
  • ISE - 9.1i
  • ISE - 9.1i sp1
  • ISE - 9.1i sp2
  • ISE - 9.1i sp3
  • ISE - 9.2i
  • ISE - 9.2i sp1
  • ISE - 9.2i sp2
  • ISE - 9.2i sp3
  • ISE - 9.2i sp4
  • ISE - 10.1
  • ISE - Legacy
  • Less