We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22318

Virtex-4/-5 - What is the minimum frequency for a PMCD clock input?


What is the minimum frequency for clock inputs to a PMCD?


There is no restriction on the minimum frequency of Virtex-4 FPGA PMCD clock inputs. This is documented in the Virtex-4 FPGA Data Sheet.
If you use the Virtex-5 FPGA PLL in PMCD legacy mode, there is a minimum input frequency specification of 1 MHz. This is mentioned in the Virtex-5 FPGA Data Sheet.
AR# 22318
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article