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AR# 22320

LogiCORE PCI Express v3.3 - Release Notes and Known Issues for 8.2i IP Update 2 (8.2i_IP2)

Description

Keywords: CORE, COREGen, CORE Generator
.
This Answer Record contains Release Notes and installation information for LogiCORE PCI Express Core v3.3.

Solution

Updates for the pci_exp_1_lane_32b_ep, pci_exp_4_lane_32b_ep, and pci_exp_8_lane_64b_ep Cores

A CORE Generator update (8.2i IP Update 2) is available for the pci_exp_1_lane_32b_ep, pci_exp_4_lane_32b_ep, and pci_exp_8_lane_64b_ep cores. This must be downloaded and installed on top of your current 8.2i design tools. For general information about this update, see (Xilinx Answer 23831). This update is located at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

Updates for the pci_exp_1_lane_64b_ep and pci_exp_4_lane_64b_ep Cores

For customers using the pci_exp_1_lane_64b_ep and pci_exp_4_lane_64b_ep, download a new zip file containing this update from the PCI Express Lounge at:
http://www.xilinx.com/pciexpress

Known Issues v3.3

- See (Xilinx Answer 24031) regarding information clock correction settings when using asynchronous links.



- PCI Express PIPE Endpoint Core does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

Previous Release Information

New Features v3.2

- Support added for ISE 8.2i.
- New cfg_dsn port; the user application drives this port with a unique 64-bit Device Serial Number.
- Includes a PCI Express Downstream Port functional simulation model as part of the user test bench.

General Information v3.2

- Power Consumed and Power Dissipation GUI parameters are now entered in decimal and not hexadecimal.
- A new input port called cfg_dsn has been added to the core; this takes the place of the Device Serial Number field that was in the GUI. The device serial number is now an input port to the core so you can change the number without having to regenerate the core. For more information on the device serial number, refer to section 7.12.2 of the PCI Express Base Specification.
- As a result of the above two changes, existing v3.1 CORE Generator XCO files do not allow generation of a v3.2 core with the same parameters. A perl script is provided so you can migrate your existing XCO file to a v3.2-compatible XCO file. This script changes the power consumed and power dissipation parameters to decimal, changes the core version to v3.2, and comments out the device serial number parameter. This script is located at:
http://www.xilinx.com/txpatches/pub/utilities/fpga/pcie_xco_ver_migrate.zip

- Existing v3.1 through v3.1.3 UCF files must be updated to include changes in v3.2 UCF files. Note that the format of timing constraints can change depending on the core that is used. Also, the hierarchical paths inside the core can change. Use the new UCF file produced with the core as a guide to update existing UCF files if designs are migrated to v3.2. An example of changes in the core's hierarchy is as follows:

PIN "pci_interface/ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST.TXPMARESET" TIG ;
to:
PIN "pci_interface/ep/BU2/U0/interface_32bit.pcie_4_lane.pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST.TXPMARESET" TIG ;

Known Issues v3.2

- See (Xilinx Answer 23225) for information on warning in simulation of the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep cores due to trn_trem_n and trn_rrem_n ports.
- Programmed Power Management and Active State Power Management are not supported in this release. The PCI Express link cannot be driven to non-D0 Power Managed state. The PCI Express Core transmitter cannot be driven to L0s, and PCI Express link cannot be driven to L1 as part of Active State Power Management.
- The PCI Express Endpoint Core does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging, and is not needed for normal operation.

New Features v3.1 Revision 3

- Support for 250 MHz sys_clk for Virtex-4FX ES4 stepping. See (Xilinx Answer 23407) for information on the usage of 125 MHz.

Obtaining v3.1 Revision 3

- This revision can be obtained at:
http://www.xilinx.com/txpatches/pub/swhelp/coregen/pci_express_v3_1_rev3.zip

Ensure that you have 8.1i SP3 IP Update 1 installed before installing this patch.

Fixed Issues v3.1 Revision 3

- CR 231602: Physical link on 4- and 8-Lane Endpoint Cores trains to 1-lane operation if PCI Express lanes are reversed and the connected downstream port supports lane reverse.
- CR 230867: Endpoint LTSSM does not transition from Configuration-Complete state to Configuration-Idle state if the connected downstream port transmits exactly 16 Logical Idle symbols, before it transmits Init FC DLLPs.

Known Issues v3.1 Revision 3

- See (Xilinx Answer 23225) for information regarding warning in simulation of the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep Cores due to trn_trem_n and trn_rrem_n ports.
- See (Xilinx Answer 23226) for information on the User Guide documentation regarding the number of transmit buffers available in the pci_exp_1_lane_32b_ep Core.
- Programmed Power Management and Active State Power Management is not supported in this release. The PCI Express link cannot be driven to non-D0 Power Managed state. The PCI Express Core transmitter cannot be driven to L0s, and PCI Express link cannot be driven to L1 as part of Active State Power Management.
- PCIe Endpoint does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is mainly used for testing and debugging, and is not needed for normal operation.

New Features v3.1 Revision 2

- Support for 8.1i SP3.
NOTE: 8.1i sp3 is required for all Virtex-4 PCI Express designs as of the revision 2 release.
- Support for Virtex-4 FX ES4 Stepping: Virtex-4 FX Cores include Calibration Block 1.4.1 to support CES4 silicon stepping.

Fixed Issues v3.1 Revision 2

- CR 226208: 3 DWORD TLP with TLP Digest (and TD bit set) presented to the 64-bit Transmit Transaction Interface is corrupted by the core.
- CR 228945: trn_rbar_hit_n bit for Memory Read 32 (MRd32) TLP is not asserted when the TLP is preceded and followed by Completion with Data TLPs (CplD).
- CR 228948: Time-out UpdateFC DLLPs for Posted and Non-Posted credit queues is transmitted more often than recommended by the specification.

Known Issues v3.1 Revision 2

- See (Xilinx Answer 23225) for information regarding warning in simulation of the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep cores due to trn_trem_n and trn_rrem_n ports.
- See (Xilinx Answer 23226) for information on the User Guide documentation regarding the number of transmit buffers available in the pci_exp_1_lane_32b_ep core.
- Programmed Power Management and Active State Power Management is not supported in this release. The PCI Express link cannot be driven to non-D0 Power Managed state. The PCI Express core transmitter cannot be driven to L0s, and PCI Express link cannot be driven to L1 as part of Active State Power Management.
- PCIe Endpoint does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is mainly used for testing and debug and is not needed for normal operation.

New Features v3.1 Revision 1

- Added 8.1i SP2 support.
- Virtex-4 FX Cores include Calibration Block 1.1.1 to support CES2 silicon stepping.

Fixed Issues v3.1 Revision 1

- PME_TO_ACK message TLP routing field corrected.
- ModelSim simulation script added.
- Corrected an issue regarding unsolicited ERR_FATAL Message TLP generated. This occurred if fatal error reporting was enabled. An ERR_FATAL Message might be generated if received Ack DLLPs were discarded as a result of CRC error and TLP Replay occurs as a result of Ack Timeout.
- Corrected an issue regarding unsolicited ERR_NONFATAL Message TLP generated. If nonfatal error reporting was enabled, ERR_NONFATAL Message TLP generated on receipt of Configuration Read Type0 TLP with Bus and Device number not equal to Bus and Device number on a previously received Configuration Write Type0 TLP.
- Reads to Device Serial Number Extended Capability Register or any user PCI Express Extended Capability register (Byte Offsets 0x400 to 0xFFF) were returning the Device and Vendor ID or all 0s when using the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep Cores. This issue has been corrected.
- Corrected an issue concerning the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep Cores incorrectly presenting the TRN_TBUF_AV output of the core to be 4 bits wide instead 5 bits wide.
- Corrected an issue concerning the pci_exp_1_lane_32b_ep or pci_exp_4_lane_32b_ep Cores incorrectly having extra TRN_RREM output and TRN_TREM input ports.
- Corrected an issue where if in CORE Generator GUI "Advanced Link Layer Settings" box labeled "Automatically calculate timer values" is unchecked, then the core incorrectly allows a value of "0" to be driven into timeout counters.

Known Issues v3.1 Revision 1

- See (Xilinx Answer 23129) for information regarding the Advanced Link Layer Setting sections of the CORE Generator customization GUI.
- See (Xilinx Answer 23176) for information on where to find the User Guide for the v3.1 Rev 1 Core.
- Programmed Power Management and Active State Power Management is not supported in this release. The PCI Express link cannot be driven to non-D0 Power Managed state. The PCI Express core transmitter cannot be driven to L0s and PCI Express link cannot be driven to L1 as part of Active State Power Management.
- PCIe Endpoint does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is mainly used for testing and debug and is not needed for normal operation.

New Features v3.1

- ISE 8.1i support.
- CORE Generator Integration.
- Port Changes: Removed cfg_cfg configuration port. The core is now customized using the CORE Generator GUI.
- PCI Express 8-lane support added.
- Includes a PIO example design for all supported cores: 1-lane, 4-lane, and 8-lane.

Known Issues v3.1

- See (Xilinx Answer 22679) regarding issues with PME_TO_ACK message routing field.
- See (Xilinx Answer 22718) regarding support of ModelSim.
- See (Xilinx Answer 22719) regarding extra ports on the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep Cores.
- See (Xilinx Answer 22721) regarding information about TRN_TBUF_AV prot width on the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep Cores.
- See (Xilinx Answer 22723) regarding information about reading PCI Express Extended Capability registers in the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep Cores.
- See (Xilinx Answer 22783) for issues regarding the "Automatically calculate timer values (Recommended)" option in Panel 7 of the CORE Generator customization GUI.
- Programmed Power Management and Active State Power Management is not supported in this release. The PCI Express link cannot be driven to non-D0 Power Managed state. The PCI Express Core transmitter cannot be driven to L0s and PCI Express link cannot be driven to L1 as part of Active State Power Management.
- PCIe Endpoint does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is mainly used for testing and debug and is not needed for normal operation.

AR# 22320
Date Created 09/04/2007
Last Updated 01/03/2007
Status Active
Type General Article