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AR# 22321

LogiCORE PCI v3.160, PCI-X v5.160, PCI v4.1, PCI-X v6.1, and PCI/PCI UCF Generator v2.1 - Release Notes and Known Issues for 8.2i IP Update 2 (8.2i_IP2)

Description

This Answer Record contains information on known issues associated with generating the following cores:

- 32-bit PCI v3.160

- 64-bit PCI v3.160

- 64-bit PCI-X v5.160

- 32-bit PCI v4.1

- 64-bit PCI v4.1

- 64-bit PCI-X v6.1

- PCI/PCI-X UCF Generator v2.1

Solution

A CORE Generator update (8.2i IP Update 3) is available for the PCI UCF Generator. This must be downloaded and installed on top of your current 8.2i design tools. Please see (Xilinx Answer 24226) for general information about this update.

This update can be found at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

NOTE: There are no updates for the PCI v3.160, PCI-X v5.160, PCI v4.1, or PCI-X v6.1 cores in this release.

PCI/PCI-X UCF Generator v2.1

- IP progress bar might appear to hang at 60%. See (Xilinx Answer 21865).

- Some UCF files will not meet timing. See (Xilinx Answer 22671).

Previous Release Information

PCI v3.160, PCI-X v5.160, PCI v4.1, or PCI-X v6.1

- See (Xilinx Answer 24171) for information regarding not being able to generate PCI32, PCI64, or PCI-X cores due to receiving "ERROR:Portability:74 - Port_Compress::UnCompress() : (Z_DATA_ERROR) input data was corrupted" when attempting to generate the core.

New Features for 8.2i IP Update 1

-This release includes new cores that target Virtex-5 devices. For PCI, the core is v4.1 and for PCI-X, the core is v6.1. Designs targeting Virtex-4, or earlier devices, must still use the v3.160 for PCI and v.5.160 for PCI-X. The v3.160 and v5.160 cannot be used in a Virtex-5 device.

-Support for Spartan-3E 33-MHz UCF generation added to the UCF Generator.

Known Issues for 8.2i IP Update 1

PCI 32-bit and 64-bit v3.160

- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.

- See (Xilinx Answer 22678) for information regarding discontinued XC2S30PQ208 and XC2S100FG456 parts.

- See (Xilinx Answer 22963) regarding commented lines in Virtex-4 UCF files.

- See (Xilinx Answer 22589) for special considerations regarding implementing PCI in a Spartan-3E.

PCI-X 64-bit v3.105

-None

PCI 32-bit and 64-bit v4.1

-Timing simulation will not work unless 8.2i sp1 has been installed because of an issue with 8.2i NETGEN producing incorrect back-annotated simulation models for PCI and PCI-X designs with 3-state outputs. Installation of 8.2i sp1 fixes this problem.

-When running MAP on PCI and PCI-X designs using 8.2i and 8.2i sp 1, an extra inverter is inserted on the core's reset path. Functional simulation is correct, but anything post-MAP will not work, including implementation in hardware. This problem is fixed in 8.2i sp2.

PCI-X 64-bit v6.1

-Timing simulation will not work unless 8.2i sp1 has been installed because of an issue with 8.2i NETGEN producing incorrect back-annotated simulation models for PCI and PCI-X designs with 3-state outputs. Installation of 8.2i sp1 fixes this problem.

-When running MAP on PCI and PCI-X designs using 8.2i and 8.2i sp1, an extra inverter is inserted on the core's reset path. Functional simulation is correct, but anything post-MAP will not work, including implementation in hardware. This problem is fixed in 8.2i sp2.

-On panel 4, of the PCI-X v6.1 GUI, users can specify the number of requested vectors for the MSI capability. Currently, users should leave this to the default of "1 Message." Selecting any other value will cause generation of the core to fail. This will be fixed in the next release, which is due in December 2006.

-On panel 4, of the PCI-X v6.1 GUI, users choose to continue the capability list at the address specified. This value can be anywhere from 80h to FFh. Currently, only numeric values can be used in this field. In other words, values such as 80, 84, 90, or 94 are valid. However, non-numeric values such as 8A, 8C, AA, or AB will cause CORE Generator to crash during generation of the core. This will be fixed in the next release, which is due in December 2006.

PCI/PCI-X UCF Generator v1.0

- IP progress bar might appear to hang at 60%. See (Xilinx Answer 21865).

- Some UCF files will not meet timing. See (Xilinx Answer 22671).

Known Issues for 8.2i

PCI 32-bit and 64-bit v3.155

- See (Xilinx Answer 22589) for special considerations regarding implementing PCI in a Spartan-3E.

- See (Xilinx Answer 22678) for information regarding discontinued XC2S30PQ208 and XC2S100FG456 parts.

- See (Xilinx Answer 22914) for information regarding Spartan-3E designs failing timing in 8.1i sp2.

- See (Xilinx Answer 22924) for information regarding PAR placement problems for Virtex-4 66 MHz designs that result in unrouted clock nets.

- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.

- See (Xilinx Answer 22963) regarding commented lines in Virtex-4 UCF files.

PCI-X 64-bit v3.105

-None

PCI/PCI-X UCF Generator v1.0

- IP progress bar might appear to hang at 60%. See (Xilinx Answer 21865).

- Some UCF files will not meet timing. See (Xilinx Answer 22671).

- PCI/PCI-X UCF Generator Customization GUI will not appear to be laid out correctly on some displays. This is a problem with the Advanced Setting pop-up or the horizontal scroll bar on the second panel under the device graphic, and occurs because system font settings are conflicting with the PCI/PCI-X GUI. To fix this issue, change the font setting to 10 pt, sans (if available).

AR# 22321
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article