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AR# 22324

LogiCORE Fibre Channel Arbitrated Loop v1.1 Core - Release Notes and Known Issues for the Fibre Channel Arbitrated Loop Core

Description

This Answer Record contains the Release Notes for the LogiCORE Fibre Channel Arbitrated Loop v1.1Core, which was released in 8.1i IP Update #1 and includes the following: 

 

- New Features in v1.1 

- Bug Fixes in v1.1 

- Known Issues in v1.1  

 

For installation instructions and design tools requirements, see (Xilinx Answer 22155).

Solution

New Features in v1.1 

 

- First release 

 

Bug Fixes in v1.1 

 

- N/A 

 

Known Issues in v1.1 

 

- The dates in the Fibre Channel Arbitrated Loop User Guide are incorrect. They should read "2006" instead of "2005". 

 

- Memory collisions occur during speed switch in the demonstration testbench. For more information on these errors, see (Xilinx Answer 22665)

 

- Verilog timing simulation causes timing errors at the beginning of the simulation. For more information on these errors, see (Xilinx Answer 22666)

 

- Setup/hold errors in the DCM_STANDBY macro are occasionally reported in timing simulation. For more information on these timing violations, see (Xilinx Answer 22667)

 

- The ucf constraint for the refclk_init period is generated with the wrong period for the Virtex-4 1/2G Core. For more information on correcting this, see (Xilinx Answer 22789)

-The example design currently uses the Virtex-4 v1.2.1 calibration block for CES2/3. To get the latest calibration block v1.2.2 for CES2/3, or to migrate to the v1.4.1 calibration block (CES4 requirement), see (Xilinx Answer 22477).

AR# 22324
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article