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AR# 22327

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Core - Release Notes and Known Issues for the Ethernet 1000BASE-X PCS/PMA or SGMII Core


This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Core, which was released in 8.1i IP Update #1 and includes the following:

- New Features in v7.0

- Bug Fixes in v7.0

- Known Issues in v7.0

For installation instructions and design tools requirements, see (Xilinx Answer 22155).


New Features in v7.0

- Support added for ISE 8.1i

- Updated Virtex-4 RocketIO attributes and clocking scheme

- Example Design includes Calibration Block v1.2.1 for the Virtex-4 FX RocketIO (tested in hardware)

- Dynamic switching capability between 1000BASE-X and SGMII standards

- Added simulation script support for Cadence IUS (NC-Sim and associated compiler)

Bug Fixes in v7.0

- CR 208621: Virtex-4 RocketIO attributes updated for ISE 7.1i SP3

Known Issues in v7.0

1. When SGMII is used at 10 Mb/s to connect two devices with 100 ppm clocks, there is potential for overflow or underflow in the RocketIO Elastic Buffer for both Virtex-II Pro and Virtex-4. For more information, see (Xilinx Answer 23319).

2. The example design currently uses the Virtex-4 v1.2.1 calibration block for CES2/3. To get the latest calibration block v1.2.2 for CES2/3 see (Xilinx Answer 22477). To migrate from the Virtex-4 v1.2.1 calibration block (CES2/3 requirement) to the v1.4.1 calibration block (CES4 requirement), install the patch provided below. For more information on the Virtex-4 calibration blocks, see (Xilinx Answer 22477).

3. Virtex-4 GT11 attributes are targeted for CES2/3. To update attributes for CES4, install the patch below.

4. Virtex-4 FX GT11 jitter errata exceeds the IEEE Std 802.3-2002 specification when using a reference clock of 125 MHz. To avoid this issue, Xilinx recommends a 250 MHz reference clock. The patch below implements this clocking scheme. For more information, see (Xilinx Answer 23392) and the Virtex-4 FX errata.

5. Virtex-4 CES2/3 requires an external clock divider for TXUSERCLK and RXUSERCLK. For CES4, you can use the internal GT11 dividers (implemented in the patch below). For more information, see (Xilinx Answer 23392).

6. The comma mask attribute used for Virtex-4 RocketIO is incorrect, but this does not affect operation. For more information, see (Xilinx Answer 23138).

7. Reset logic for GT11 should not be clocked off a clock generated from the GT11. The version 7.0 rev1 patch used TXOUTCLK1. This issue was resolved in v7.1 by moving all of the reset logic into the wrapper file and using the DCLK for the calibration block; v7.1 of the core is available in 8.2i IP Update 1.


To update to CES4 and resolve issues 2, 3, 4, 5 and 6 from the list of issues above, apply the following patch to the Xilinx ISE installation with the 8.1i Service Pack 3 and IP Update #1:


1. Install the patch by extracting the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.


Determine the Xilinx installation directory by entering the following at the command prompt:

echo %Xilinx%

UNIX or Linux

Determine the Xilinx installation directory by entering the following:

echo $Xilinx

NOTE: You may be required to have system administrator privileges to install the patch.

2. After installing the patch, regenerate the Ethernet 1000BASE-X PCS/PMA or SGMII Core from CORE Generator. The core and supporting files produced will contain the updates mentioned above.

AR# 22327
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article