This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v4.1 that was released in 8.1i IP Update #1, and includes the following:
- New Features in v4.1
- Bug Fixes in v4.1
- Known Issues in v4.1
For installation instructions and design tools requirements, see (Xilinx Answer 22155).
New Features in v4.1
- Support added for 16-bit client mode
- Example design added
- UCF file and implement scripts added to synthesize and implement the Example Design using ISE 8.1i
- Simulation scripts added for Cadence IUS (NC-Sim and associated compiler)
- SGMII and 1000BASE-X Example Designs includes Calibration Block v1.2.1 for the Virtex-4 FX RocketIO (tested in hardware)
Bug Fixes in v4.1
Known Issues in v4.1
1. v4.1 of the wrapper files targeted CES2/3 silicon. v4.2 of the wrapper files has now been released and should be used if targeting CES4. This version or later versions have necessary calibration block and attribute updates for CES4. You can find the v4.2 release notes at (Xilinx Answer 23503).
2. Verilog back-annotated simulations might be incorrect when using the GMII and RGMII interfaces. The problem is that IDELAYs are used in the design, but the Verilog SimPrim model for the IDELAY component is incorrect. This issue is fixed in 8.1i sp2; for more information, see (Xilinx Answer 22644).
3.The example design currently uses the Virtex-4 v1.2.1 calibration block for CES2/3. To obtain the latest calibration block v1.2.2 for CES2/3, or to migrate to the v1.4.1 calibration block (CES4 requirement), see (Xilinx Answer 22477).
4. If you have selected the Tri-Speed GMII or MII configurations (in both VHDL and Verilog), there is a mistake in the connection of signals in the "<component_name>_top" file. For more information and a way to work around this issue, see (Xilinx Answer 23006). The problem is fixed in the patch below.
5. The EMAC is never able to Auto-Negotiate and appears frozen or stuck in a loop. This problem is the result of an incorrect connection in the wrapper file. For information and a way to work around this issue, see (Xilinx Answer 23303). This problem is fixed in the patch below.
6. Header file "xv4emac_l.h" has incorrect mask values. For information and a way to work around this issue, see (Xilinx Answer 23306). This problem is fixed in the patch below.
7. Incorrect values on RocketIO MGT. The comma values for the RocketIO MGT were technically incorrect. For more information and a way to work around this issue, see (Xilinx Answer 23305). This is corrected in the patch below.
8. When SGMII is used at 10Mb/s to connect two devices with 100ppm clocks, there is potential for overflow or underflow in the RocketIO Elastic Buffer for both Virtex-II Pro and Virtex-4. For more information, see (Xilinx Answer 23319).
9. Virtex-4 FX GT11 jitter errata exceeds the IEEE Std 802.3-2002 specification when using a reference clock of 125 MHz. To avoid this issue, Xilinx recommends a 250 MHz reference clock. For information on switching to a 250 MHz reference clock, see (Xilinx Answer 23612) and the Virtex-4 FX errata.
To resolve issues #4, #5, #6, and #7 from the list of General Issues above, apply the following patch to the Xilinx ISE installation with 8.1i Service Pack 3 and IP Update #1:
Install the patch as follows:
1. Extract the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You may be required to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the Embedded Tri-mode Ethernet MAC Wrapper v4.1 Core from CORE Generator. The wrapper files produced will contain the fixes listed above.