I have generated a CORE Generator LogiCORE using the Verilog flow, and the VEO template file and the Verilog simulation wrapper filers have been created.
I cannot find a Verilog simulation model, and I receive the following errors when attempting to simulate:
When I perform a Verilog behavioral simulation of the Pipeline Divider Core v.3.0, the following error occurs:
There are several cores that do not have Verilog behavioral models.
The supported language for behavioral simulation is VHDL.
If your simulator does not support multiple languages, you can work around this issue by generating a Verilog structural model with ISE 7.1i or above.
To generate a Verilog model for simulation, follow these steps:
1. Go to Project Options.
2. From the Generation tab, select Verilog as the design flow and Structural as the model type.
On generation, a UniSim-based model of the divider is created.
Note: The CORE Generator Structural flow is advised only for the cores where the data sheet indicates that it should be used.
For Cores where the Structural Netlist is not available, you will need to see (Xilinx Answer 8065).
Another way to work around this issue is to use the post-translate (post-NGDBuild) gate-level Verilog netlist generated from the EDIF or NGC netlist to run the simulation.
For more information, please see (Xilinx Answer 8065).