We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2234

M1.5, M1.4 MAP/NGDBUILD, LogiBLOX - Pin mismatch between block<name>... at pin<name>...


Keywords: MAP, NGDBuild, unexpanded, pin mismatch, LogiBLOX,
bus delimiter

Urgency: Standard

General Description:
WARNING:0 - Pin mismatch between block 'addsub1', TYPE='addsub32',
and file '/xilinx/fpga/design/addsub32.ngo' at pin 'A<31>'.



When the above warning or error occurs while running NGDBUILD
on a design that contains a LogiBLOX module, frequently the
cause is a mismatch between the bus pin dimension separator
(bus delimiter) used in the LogiBLOX module netlist and the
delimiter used in the block that contains it (i.e., the
bus element may be named "mybus<3>" in the LogiBLOX .NGO
(or .NGC) file, but may exist as "mybus(3)" in the design).

The solution is to ensure that the bus delimiter used in the
LogiBLOX module matches the one used in the symbol or
HDL instantiation that references the module. In LogiBLOX,
this can be done by either choosing the appropriate Vendor
from the Setup window (Viewlogic, Synopsys, Mentor, or
Foundation), or choosing "Other" for vendor and selecting the
correct Bus Notation setting from that window.


To review what the settings were last used to generate a given
module, you can check the settings in the logiblox.ini file.


Make sure that the pin *names* on the symbol block or HDL
instance that references the LogiBLOX module match the port
names on the LogiBLOX module itself.

- If using a HDL tool, paste the contents of the
VHDL or Verilog template (.vhi and .vei, respectively) into
your code to instantiate the module.

- If you are manually generating a symbol for the LogiBLOX
module (necessaryfor some schematic entry tools), check
to make sure that pin names match precisely.

Also note:

- Pin names should be in upper case.
- The names of the pins for a given module can be found in its
.mod file.
- The bus notation used in the generated module can be found
in the .ini file if you are uncertain which setting was
used to generate your module.

AR# 2234
Date 02/08/2001
Status Archive
Type ??????
Page Bookmarked