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AR# 22355

9.1i NetGen/PrimeTime - Although cell or net arcs are not annotated, this does not mean that the timing analysis is not accurate


When using PrimeTime, I typically expect to see that all cell arcs and net arcs in the netlist are annotated using the delay information in the SDF file. The PrimeTime Tables indicate that none of my net arcs to Primary Outputs are annotated or a large number of cell arcs are not annotated. Is this accurate?


Although this might be true in the ASIC world when SDF file contains IOPATH and INTERCONNECT constructs, this is not necessarily true for Xilinx flow where there are IOPATH and PORT constructs in SDF and LUT4MUX16 cells. 
For example: 
1. PrimeTime is expecting an interconnect or port delay for the output port itself. But, for the Xilinx flow, the output delay is modeled in the IOPATH for the output buffer and in the IOPATH and PORT delays in other buffers before the output buffer. 
It is possible to have none of the output timing arcs annotated while the effective delay is on the annotated on the IOPATH and PORT delays of the elements that drive the output net, and have this result in accurate timing analysis--matches the TRACE. 
2. Since all the LUTs are replaced by LUT4MUX16, a large number of cell arcs are associated with these cells that are not annotated because of the usage of this cell.
AR# 22355
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article