UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22368

Spartan-3E - Special considerations for using the Input Delay Element

Description

Keywords: support, software, IDELAY, guidelines

When using ISE 7.1i, 8.1i, or 8.1.1i, use special consideration when using the Input Delay Element because the Xilinx design tools are changing the way the Input Delay Element is handled in 8.1.02i.

Solution

The Spartan-3E device has a programmable input delay. ISE 8.1i Service Pack 1 and Service Pack 2 contain changes that will significantly affect the use of this feature. Xilinx strongly recommends use of the following guidelines until Service Pack 2 is available in February 2006:

- Always specify an input delay value number for registered inputs (IFD_DELAY_VALUE).
- Do not use the highest settings. Limit choices to IBUF_DELAY_VALUE=(0 to 12) and IFD_DELAY_VALUE=(0 to 6).
- Re-verify timing if you are re-generating a bitstream with ISE 8.1i Service Pack 2.
- If the same input pin has both combinatorial and registered paths, limit the values to legal combinations.

Always specify an Input Delay value number for registered inputs
Registered inputs (IFD) default to IFD_DELAY_VALUE=AUTO. AUTO is set to "5" in ISE 7.1i and ISE 8.1i. The delay is intended to add just enough data delay to avoid a hold time, but the value of "5" is more than is necessary for most situations. The AUTO setting will be set to a value less than "5" in future Service Packs to provide better timing results.

To avoid being affected by this change and to obtain the best results now, set the IFD_DELAY_VALUE to an appropriate number to meet your own specific timing requirements. In many cases, a value of "1" is sufficient to avoid any hold-time requirements.

Do not use the highest settings
Do not use IBUF_DELAY_VALUE=(13 to 16) or IFD_DELAY_VALUE=(7 to 8). These values are allowed in ISE 7.1i and ISE 8.1i and are shown in the FPGA Editor, but they will not be supported by the silicon. DRC changes in ISE 8.1i Service Pack 1 will prevent the use of these settings. Limit IBUF_DELAY_VALUE to the range from 0 to 12 and limit IFD_DELAY_VALUE to the range from 0 to 6.

Re-verify timing if you are re-generating a bitstream with ISE 8.1i Service Pack 2
When ISE 8.1i Service Pack 2 is released, the delay values will change for some of the input delay settings, both as a result of a new speed file and due to changes in the way the software maps input delay settings to the silicon. Designs implemented before ISE 8.1i SP2 do not need to be re-implemented since they will continue to meet the timing specified in the original ISE 8.1i or SP1 software. Designs that are re-implemented after installing Service Pack 2, even if only through BitGen, might generate a different implementation and timing must be re-verified for the I/O.

All input delay values on the right side of the device will change, except for the "0" settings. These changes are expected to result in some delays increasing and others decreasing. All changes are expected to be less than 1 ns.

In addition, the larger input delay settings will result in longer delay values being reported for the other three sides of the device (left, top, and bottom). The IBUF_DELAY_VALUE settings of 8-12 will be slower by about 0.7 ns. The IFD_DELAY_VALUE settings of 5 or 6 will be increased by about 0.6 ns.

If the same input pin has both combinatorial and registered paths, limit the values to legal combinations
A single input can use both the combinatorial and registered paths through the IOB. Since the pre-delay mux is common to both paths, only certain combinations of delay value settings are allowed. Some combinations allowed now will no longer be allowed after Service Pack 1.

Legal combinations include:

IBUF_DELAY_VALUE.......IFD_DELAY_VALUE
0...................................................Any
Any.................................................0
1-6.................................................0-3
7-12...............................................4-6
AR# 22368
Date Created 11/10/2005
Last Updated 01/08/2006
Status Active
Type General Article