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AR# 22380

Precision - "Error: File "tenths.vhd", Line 33: Unsupported Clocking Style: Dual edge for clock 'CLOCK' is not supported."

Description

Keywords: synthesis, CoolRunner

Urgency: Standard

General Description:
How can I infer the dual-edge flip-flop available in the CoolRunner-II parts?

Solution

Precision currently does not support HDL code that would infer a dual-edge triggered flip-flop. The only solution is to instantiate the dual-edge triggered flip-flop primitive for the CoolRunner-II device:

VHDL:

component FDD
port (
Q : out STD_LOGIC;
C: in STD_LOGIC;
D : in STD_LOGIC
);
end component;

:
;

u1 : FDD port map (D => din, C => dual_edge_clock, Q => qout);


Verilog

FDD u1 (.D(din), .C(dual_edge_clock), .Q(qout));

AR# 22380
Date Created 11/14/2005
Last Updated 04/30/2007
Status Archive
Type General Article