We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22381

LogiCORE SPI-3 PHY v4.1 - Release Notes and Known Issues for the SPI-3 PHY Layer Core


This Release Note is for the SPI-3 (POS-PHY L3) Physical Layer v4.1 Core released in 8.1i IP Update 1 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 22155).

This core is automatically delivered with ISE8.2i DVD Release.


New Features in v4.1

- Support added for ISE 8.1i

- NC-Sim Support added

Bug Fixes in v4.1


Known Issues in 4.1

-(Xilinx Answer 22717) The example testbench may send packets beyond maximum selected.

-(Xilinx Answer 22027) PAR displays: "INFO:Par:62 - Your design did not meet timing."

-(Xilinx Answer 22042) PAR places the clock pin and DCM on opposite sides of the chip, causing timing failures.

-(Xilinx Answer 22043) "ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed."

-(Xilinx Answer 22028) BitGen results in "ERROR:PhysDesignRules:755 - IOB comp <TX_DTPA(16)> at location <AH34> is VCCO."

-(Xilinx Answer 22053) When simulating design example, data might be sent to channels not used by the core.

AR# 22381
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article