AR #22391 - 8.1i Simulation, Virtex-4 - Initialization of FIFO16 WRCOUNT and RDCOUNT in the simulation model is not matching the hardware
8.1i Simulation, Virtex-4 - Initialization of FIFO16 WRCOUNT and RDCOUNT in the simulation model is not matching the hardware
| AR# | 22391 |
| Part | SW-Sim Libraries |
| Last Modified | 2008-10-16 00:00:00.0 |
| Status | Archive |
| Keywords | ModelSim, NC-VHDL |
Description
Keywords: ModelSim, NC-VHDL
When I perform a simulation of the FIFO16, the initial values of the WRCOUNT and RDCOUNT show up as "0" in the simulation model. In the hardware, these values are initialized to "0xFFF" (FIFO Depth).
Why is this occuring?
Solution
This is an issue with the simulation models. The values for the counters should be consistent between the simulation models and hardware.This issue is fixed in the latest 8.1i Service Pack, available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.