We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22391

8.1i Simulation, Virtex-4 - Initialization of FIFO16 WRCOUNT and RDCOUNT in the simulation model is not matching the hardware


Keywords: ModelSim, NC-VHDL

When I perform a simulation of the FIFO16, the initial values of the WRCOUNT and RDCOUNT show up as "0" in the simulation model. In the hardware, these values are initialized to "0xFFF" (FIFO Depth).

Why is this occuring?


This is an issue with the simulation models. The values for the counters should be consistent between the simulation models and hardware.

This issue is fixed in the latest 8.1i Service Pack, available at:
The first service pack containing the fix is 8.1i Service Pack 1.
AR# 22391
Date Created 09/04/2007
Last Updated 10/16/2008
Status Archive
Type General Article