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AR# 22392

LogiCORE SPI-4.2 (POS-PHY L4) - SysClk for slave clocking mode should not come from another Sink core


General Description: 

When using the SPI-4.2 Core with "slave clocking", the Source core will be created without the clocking scheme, and it will be up to you to provide your own clocking scheme. See the "Source Clocking" section of the SPI-4.2 User Guide for more information. The User Guide, however, does not mention where the clocking should come from.


The slave clocking is recommended for designs requiring multiple instances of the SPI-4.2 Core. By generating one Source core with master clocking scheme and the rest of the Source cores in slave clocking scheme, you should be able to share the clocking logic among all the Source cores. 


However, the Source core in the slave clocking mode, should never get its clocking supply from any of the Sink cores (i.e., RDClk_GP). This will introduce significant jitter to the core, and potentially cause functionality issues. The main source of SysClk should be from the low jitter off-chip differential output oscillator or other high-quality, low jitter clock source.

AR# 22392
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article