What are some of the differences between the IBM and Xilinx implementations of the OPB CoreConnect?
OPB devices developed by Xilinx do not support dynamic bus sizing and, consequently, do not use the following legacy signals: Mn_dwXfer, Mn_fwXfer, Mn_hwXfer, Sln_dwAck, Sln_fwAck, and Sln_hwAck.
Since OPB devices developed by Xilinx are byte-enable only, the Mn_beXfer and Sln_beAck signals are not required and so they are not used.
The signals required for masters and slaves are separate from the signals present in the OPB interconnect. The OPB interconnect (the OR gates and other logic required to connect OPB devices) supports the full OPB V2.1 specification (i.e., all signals are present). Thus the OPB interconnect does not limit a design to byte-enable devices and supports designs in which a mix of byte-enable legacy and OPB V2.0 devices are present. The bus interconnect does not limit the use of any feature of the V2.1 specification.
Refer to the Processor IP Reference Guide for additional details on creating systems using these signals.