We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22428

10.1 EDK- How do I create a custom OCM block RAM?


How do I create a custom OCM block RAM?


Basically, you connect your own block RAM to the block RAM controller as follows: 


1. Create a core from your modified block RAM block "dsocm_bram_elaborate.vhd." 

2. Make sure the MPD file does not contain the option special=bram. 

3. Connect the block RAM to the DS OCM block RAM controller in the MHS. 

4. Make sure the DSOCM block RAM controller MPD file does not contain the option special=bram_cntrlr. This option stops PlatGen from automatically connecting a data width matched block RAM. 


The DSOCM block RAM controller PCORE directory is in "$EDK\hw\XilinxProcessorIPLib\pcores\dsbram_if_cntlr_v3_00_a\data". 


The following is an example of the block RAM BLOCK PCORE directory/files: 




In this directory, the MPD file contains the "option special=bram" parameter. 


Remove it from your modified block RAM.

AR# 22428
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article