My design fails during timing-driven mapping with the following error:
"ERROR:Place:543 - Due to placement constraints, the following 1 components
cannot be placed. The relative offsets of the components are shown in
brackets next to the component names.
FF mp4i_core_u0/mac_pkt_hdr_proc_u0/fr_cpu_out_port (0, 0)"
I have tried to find the listed component name in my design so that I can analyze the failing constraints, but it does not exit.
This failure is occurring in a placement algorithm that involves the "physical design." The names of the physical components are derived from output net names, not from the associated instance names in the "logical design." This logic can be identified by searching for the net name and identifying the logic that drives it.