UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22451

7.1i FPGA Editor, fpga_edline - setattr results in DRC errors

Description

When I use the setattr commands in a script from FPGA Editor or fpga_edline to edit MGT components, the following error occurs: 

 

"#ERROR:PhysDesignRules:792 - Illegal configuration for block...."

Solution

To work around this issue, use Edit Block in the FPGA Editor GUI to make the changes.

AR# 22451
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article