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AR# 22471 Virtex-4 FX RocketIO Serial Transceivers - Static Operating Behavior

Keywords: errata, inactive, MGT

This Answer Record contains detailed information related to the RocketIO MGT Static Operating Behavior described in EN014 (Errata for Virtex-4 FX CES2 and CES3 devices) and EN042 (Errata for Virtex-4 CES4 devices).

All information in this Answer Record applies equally to CES2, CES2V2, CES3, CES3V2, and CES4 devices, except for the associated Calibration Block that is required for some work-arounds. To determine the appropriate Calibration Block version for each silicon version, see (Xilinx Answer 22477).

Overview

Transceivers might cease to correctly transmit and receive data under the following conditions:
- Power has been applied to the FPGA.
- Transitions are not occurring in the transmit and/or receive directions.
- The first two conditions listed above persist for more than 400 cumulative hours at 85C Tj or more than 2,000 cumulative hours at 60C Tj.

This is a concern only for transceivers that are expected to transmit or receive data in the future. Transceivers that will never be used do not require any action.

If your system meets all three conditions listed above for one or more of the transceivers used in your Virtex-4 FX device, the work-arounds outlined below must be used.

Work-arounds

There are four sets of static design configurations that require work-arounds:

1. Null FPGA: FPGA is powered but unconfigured.

Solution A: Do not power the FPGA until you are ready to configure.

Solution B: Load a temporary MGT null bitstream into the FPGA until you are ready to configure with the user-designed bitstream. The MGT null bitstream puts every MGT in the device into a safe activity mode. These bitstreams are available at:
http://www.xilinx.com/txpatches/pub/utilities/fpga/v4fx_null_bitstreams.zip
*NOTE: This file was updated on 8/10/07 to include V4FX40 and V4FX140.

(The above link will prompt you to log in to your Xilinx.com account and accept a license agreement. After doing so, click the "Download Design File" link.)

2. Null MGT Tile: Both MGTs in a tile will be used in the future, but neither MGT is instantiated in the current design.

Solution: Use a drop-in macro for both MGTs in each tile. The macro will put each individual MGT into a safe activity mode. These macros are available at:
http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?iLanguageID=1&ipoid=24332297&category=-1210767&filename=Null_Tile.zip&file=539

(The link above will bring up a page prompting you to log in to your Xilinx.com account and accept a license agreement. After doing so, click the "Download Design File" link.)

3. A or B Only: Both MGTs in a tile will be used in the future, but only one MGT is instantiated in the current design.

Solution: Use the appropriate Calibration Block. See (Xilinx Answer 22477).

4. Inactive: One or both MGTs in a tile will be used in the future and are instantiated in the design, but are not currently transmitting and receiving data.

Solution: Use the appropriate Calibration Block. See (Xilinx Answer 22477).

Frequently Asked Questions

Q: For condition #1, exactly which power supplies are of concern?
A: VCCINT
AVCCAUXRX (both A and B)
AVCCAUXTX
AVCCAUXMGT
VTTX (both A and B)
VTRX (both A and B)

Q: What supply voltages yielded the data points in Condition #3?
A: VCCINT: 1.2V
AVCCAUXRX (both A and B): 1.1V (CES2/3) and 1.2V (CES4)
AVCCAUXTX: 1.1V (CES2/3) and 1.2V (CES4)
AVCCAUXMGT: 2.5V
VTTX (both A and B): 1.5V
VTRX (both A and B): 1.5V

Q: If the design work-arounds are implemented, will the operating life of the MGTs be adversely affected?
A: No. The operating life will conform to general expectations for CES silicon.

Q: Should I be concerned about MGTs that I will never use?
A: No. MGTs that will never be used do not require any action. These unused MGTs may no longer operate as specified, but they will not affect any other MGT in the FPGA or any other part of the FPGA.

Q: What are the symptoms of an MGT that has been damaged by the Static Operation Condition?
A: An important fact to recognize with a Static Operation failure is that it affects parts that have worked error-free in the past. The following symptoms were observed as failures in static operation testing:

- A device that has worked error-free (0 BER) in the past and shows a sudden increase in Bit Error Rate with no change in configuration stream, or the board. The symptoms are more likely to occur at lower temperatures and lower AVCCAUXRX.
- A device that has worked error-free (0 BER) in the past and suddenly fails to lock (RXLOCK stays low) with no change in configuration stream, or the board.

These symptoms are similar to common problems caused by MGT attribute, setup, or board problems. If you think a part has been damaged by the Static Operation Condition, open a support case with Xilinx Technical Support so the issue can be properly debugged.
AR# 22471
Date Created 09/04/2007
Last Updated 05/15/2008
Status Active
Type
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