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AR# 22472

MIG v1.7 - Why does the MIG-generated ".ucf" set both SSTL18_I and SSTL18_II in the same I/O bank?

Description

Keywords: SSTL18, Class I, Class II, SSTL18_I, SSTL18_II, MIG, DDR, SDRAM

When I use MIG to generate a DDR2 SDRAM controller, the generated ".ucf" contains IOSTANDARD constraints that mix SSTL18_I and SSTL18_II in the same I/O bank. Is this correct?

NET "cntrl0_DDR2_DQ[*]" IOSTANDARD = SSTL18_II;
NET "cntrl0_DDR2_A[*]" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_BA[*]" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_RAS_N" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_CAS_N" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_WE_N" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_CS_N[*]" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_ODT[*]" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_CKE[*]" IOSTANDARD = SSTL18_I;
NET "cntrl0_DDR2_DM[*]" IOSTANDARD = SSTL18_I;

Solution

Yes, this is correct. Looking at the specifications of SSTL18_I and SSTL18_II in the Virtex-4 FPGA User Guide, the specifications are exactly the same, except that SSTL18_I is unidirectional and SSTL18_II is bidirectional. Since DQ is used as bidirectional, it is specified as SSTL18_II in the generated UCF.
AR# 22472
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article