| AR# | 22473 |
| Part | SW-Netgen |
| Last Modified | 2008-11-18 00:00:00.0 |
| Status | Archive |
| Keywords | same, edge, timing, SimPrim |
Keywords: same, edge, timing, SimPrim
If I use an ODDR primitive to perform Tristate control in my design and set up the ODDR primitive to operate in "same edge" mode as described in the Virtex-4 User Guide:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=User+Guides/FPGA+Device+Families/Virtex-4
I see that the Post-PAR timing simulation is not working correctly. It seems an incorrect simulation model has been generated for this part of the design.