UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22473

7.1i NetGen - Incorrect simulation model generated for ODDR Tristate control primitive

Description

Keywords: same, edge, timing, SimPrim

If I use an ODDR primitive to perform Tristate control in my design and set up the ODDR primitive to operate in "same edge" mode as described in the Virtex-4 User Guide:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=User+Guides/FPGA+Device+Families/Virtex-4

I see that the Post-PAR timing simulation is not working correctly. It seems an incorrect simulation model has been generated for this part of the design.

Solution

This issue affects only the ODDR primitive when used for Tristate control and with the "same edge" attribute attached.

This issue is fixed in ISE 8.1i Service Pack 3.

AR# 22473
Date Created 09/04/2007
Last Updated 11/17/2008
Status Archive
Type General Article