What does the following error mean?
"ERROR:Xst:772 - "Attribute is not authorized : 'succ'."
The following is my example code:
============================
type state_type is (s0, s1);
signal state : state_type;
begin
process (clk, reset)
begin
if (reset = '1') then
outdata <= '0' ;
state <= s0;
elsif rising_edge(clk) then
if (flag = '1') then
state <= state_type'succ(state);
else
state <= s0 ;
end if;
end if ;
end process ;
=================================
The VHDL LRM does not allow you to access user-defined attributes in this manner; consequently, the error message is correct. The LRM allows only the ability to access predefined attributes.
To eliminate this error, you can write your code as follows:
=============================================================
type state_type is (s0, s1);
signal state : state_type;
begin
process (clk, reset)
begin
if (reset = '1') then
outdata <= '0' ;
state <= s0;
elsif rising_edge(clk) then
if (flag = '1') then
state <= s1;
else
state <= s0 ;
end if;
end if ;
end process ;
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