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AR# 22499

Virtex-4 FX - RocketIO Wizard v1.0 Release Notes and Known Issues


This Answer Record outlines release details for the Virtex-4 RocketIO Wizard v1.0.

NOTE: RocketIO Wizard v1.2 is available; see (Xilinx Answer 23897) for details.

RocketIO Wizard v1.1 release information is available in (Xilinx Answer 22845).


Supported Operating Systems

All platforms supported by ISE 8.1i are supported.


1. Ensure that you have an account at Xilinx.com. You can create an account by clicking on the Login link at:

2. Ensure that you have installed ISE 8.1i Service Pack 2 or later. You can download the ISE Service Pack at:



NOTE: Do not interrupt the installation process. During the process, you must accept various pop-up messages. If you have other windows open, the pop-ups might be hidden behind these windows.

Method 1

Use this method if you are behind a firewall and do not know your proxy settings:

1. Browse to:

2. Click the Download link near the top.

3. Set ISE IP Update for the Download Type.

4. Set 8.1i for the ISE Version.

5. Select the appropriate Operating System.

6. Click Search.

7. Several ZIP files are offered for download.

8. Download all the ZIP files that appear under IP Update.

9. Unzip the ZIP file into the directory representing the installation of ISE 8.1.

10. The unzip step is best done through a utility like WinZip. If you do not have a ZIP utility, proceed as follows:

In UNIX shell on Linux:

$Xilinx/bin/lin/unzip -d $Xilinx zip-file-name

In a UNIX shell on Solaris:

$Xilinx/bin/sol/unzip -d $Xilinx zip-file-name

In a Windows command prompt:

%Xilinx%/bin/nt/unzip -d %Xilinx% zip-file-name

(In the above, $Xilinx or %Xilinx% represents the location of your ISE 8.1 installation.)

Method 2

This method is highly automated, but it requires you to know your proxy settings if you are behind a firewall.

1. Launch CORE Generator by selecting Start -> Xilinx ISE 8.1 -> Accessories -> CORE Generator from the Windows Start menu.

2. When the CORE Generator GUI opens, select Tools -> Updates Installer from the menu bar. You might need to create a CORE Generator project.

3. CORE Generator displays a warning that it will exit after the installation is complete. Click the Accept button.

4. If you are behind a firewall, a dialog box appears in which you enter the appropriate proxy settings.

5. The IP Updates Installer opens and displays a list of the available IP Update packages that apply to ISE 8.1.

6. You might want to click the documentation link to get more information about each available update.

7. To obtain this release, select ISE 8.1i Virtex-4 RocketIO Wizard 1.0.

8. After making your selections, click the Install Selected button.

9. The program might indicate that certain other installations are required, accept these informational dialogs.

10. A dialog box might appear asking you to enter your support.xilinx.com User ID and password, enter the requested information.

11. CORE Generator downloads and installs the requested products, and exits.

Verifying Installation

Launch CORE Generator with suitable project settings and browse to FPGA Features and Design -> IO Interfaces -> RocketIO Wizard 1.0 to verify that the core was correctly installed.

New Features

- Custom wrappers can be created to configure the RocketIO MGT.

- The following protocols can be used to configure the MGT or be used as templates for custom protocols:

---- Gigabit Ethernet

---- OC-48

---- GPON

---- PCI Express

---- XAUI

---- Aurora

- Virtex-4 FX Engineering silicon versions are supported with appropriate analog settings and calibration blocks when appropriate.

- Produces an example design and testbench with each custom wrapper, along with scripts to use them.

- The example design includes ChipScope modules to monitor the custom wrapper in hardware.

- The following Virtex-4 RocketIO features can be incorporated into custom wrappers:

---- 1 byte, 2 byte, or 4 byte data path width

---- Line rate between 622 Mb/s and 6.25 Gb/s, using analog or digital clock-data recovery

---- Programmable comma alignment, channel bonding, and clock correction

---- TX synchronization for minimal TX skew

---- Buffer bypass modes for reduced latency

---- TX and RX CRC blocks

---- Flexible placement and clocking options

---- Optional encoding/decoding

---- Optional internal AC coupling

---- Lock to reference option for over-sampling protocols

---- OOB Signaling

---- Loopback

Known Issues

- Devices supporting 64B66B were not available at development time. As a result, 64B66B options have not been tested in hardware.

- Multi-lane protocol files, such as XAUI, might not turn on all required MGTs in some packages. If the wrapper is missing lanes, re-customize it and select the missing MGTs explicitly on page 2.

- Page 2 (the Placement customization screen) allows unbonded MGTs to be selected on the XC4VFX60 in the FF672 package. MGTS X0Y0, X0Y1, X1Y0, and X1Y1 are not connected to external pins: re-customize if these MGTs are selected and bonded MGTs are required.

- Configurations where the TX line rate does not match the RX line rate have not been heavily tested, and might not work.

- Example designs for configurations using different data widths for TX and RX might not function.

- Be careful to use run lengths supported by the selected silicon version when selecting no encoding/no decoding on page 3.

- The example designs provide little support for CRC. The wrapper configures the CRC blocks, but additional work is required to test and connect them.

- If the comma alignment boundary (page 4) is smaller than the data path width, the MGT can align incoming data to multiple positions. The example design does not account for this, and might indicate errors even though data is received correctly.

- The example design does not currently include blocks to demonstrate Channel Bonding and Clock Correction.

- OOB signaling is not supported in simulation.

- The GT11 SmartModel produces RX Disparity errors due to rounding problems for some reference clock periods. If the MGT wrapper locks successfully in simulation, but shows numerous disparity errors, edit testbench/example_tb.v(hd), and increment or decrement the REFCKL period by 0.01.

AR# 22499
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article