UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22504

XST - How can I make my "include" file from the top level visible in the submodule?

Description

How can I make my "include" file from the top level visible in the submodule?

Solution


It is not possible to make the "include" file from your top level visible in the submodule because FPGA synthesis tools perform a bottom-up compilation.

For this reason, it is best to place the "include" in the lowest module of your design, as this will ensure that it will be propagated to the top level as well.

In Project Navigator there is also an option to include the Verilog file globally.
AR# 22504
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article