We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22521

LogiCORE Aurora v2.4 - Release Notes


This Release Note is for the v2.4 COREGen Aurora released in 8.1i IP Update #1. The following information is covered: 
- New Features 
- Bug Fixes 
For installation instructions and software/tool requirements, see (Xilinx Answer 22155).


New Features  
1. Added support for ISE 8.1i  
Bug Fixes 
1. CR 207154 - PMA_INIT and INIT_CLK are LOC'ed incorrectly in the generated UCF file  
2. CR 207247 - Invalid RX_D width is generated for 4-byte streaming simplex configurations  
3. CR 209737 - TX buffer overflow error condition observed in simulation  
4. CR 212905 - Superfluous RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD parameters  
5. CR 214838 - SIMPLEX_PARTNER testing issue  
6. CR 216123 - Incorrect REFCLK frequencies for 2.5 Gbps line rate displayed in customization GUI  
7. CR 220222 - Issues with UCF file generated for 4VFX20
AR# 22521
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article