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When I run behavioral simulation on designs that include CORE Generator, EDK, or Architecture Wizard IP cores, the core is not bound.
ISE Simulator issues the following warning:
"WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst <instance name> of Component <core name>"
ModelSim issues the following warning:
"# ** Warning: (vsim-3473) Component '<Instantiated IP core name>' is not bound."
After receiving the warning, the simulation continues. However, signals associated with the output of the core do not toggle correctly, as the core outputs are undefined.
This warning appears if the ".xco" file is not added to the simulation view of the Project Navigator Project.
To verify that a CORE Generator core (or any source file) has been added to the simulation view, perform the following:
Also, verify that either the ".v" or ".vhd" (depending on the "View Instantiation Template" language setting for the core) exists in the project directory.
Xilinx includes a precompiled version of the XilinxCoreLib library for ISE Simulator with the ISE softwareinstall (8.1i and later). Subsequent IP updates also contain updates to the precompiled XilinxCoreLib library to include the latest cores.
For instructions on obtaining or compiling the XilinxCoreLib library for ModelSim or other third-party simulators, see (Xilinx Answer 15338).