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AR# 22563

Virtex-4 PAR - "ERROR:Place:120 - There were not enough sites to place all selected components" about DSP slices

Description

When running PAR on my Virtex-4 design, I receive the following messages.

"WARNING:Place:119 - Unable to find location. MULT component

U_0_uv0scale/uv0hvscaler_lbw/uv0P3PlainLeeNRCalc/un4_temp_x5y3_mx_rnd[17:0]

not placed."

"ERROR:Place:120 - There were not enough sites to place all selected components."

I have seen (Xilinx Answer 22067) and know that the message refers to DSP48 components. According to my MAP report, I am using less than 100% of the DSP48 components in my device. They cannot be placed. Why?

Solution

DSP48 components within a tile share a C input bus. This means that unless you have 50 pairs of DSP48 components that share the same C inputs, you will not be able to use 100% of the DSP48s in a device.

For more information on the shared resources in a DSP tile, please see the XtremeDSP for Virtex-4 FPGAs User Guide:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-4

Starting in 8.1i, XST has an option to control the DSP Utilization Ratio. This will allow you to control the number of DSP48 components inferred and prevent these placement issues.

AR# 22563
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article