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AR# 22588

8.1 CORE Generator - "ERROR:sim:158 - Tcl error detected while configuring symbol pins"

Description

Keywords: generate, finish, manage cores, ISE, Project Navigator, symbol, CORE Generator

When I try to generate specific cores from within Project Navigator (e.g., SPI-4.2 Lite), the following Tcl error occurs:

"ERROR:sim:158 - Tcl error detected while configuring symbol pins."

The following is what it looks like from the Project Navigator console:

Customizing IP...
Finished Customizing.
Generating IP...
WARNING:sim:99 - The Implementation File Type <Edif> is not valid for this core. Overriding with File Type <ngc>.
WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this core. Overriding with File Type <structural>.
ERROR:sim:158 - Tcl error detected while configuring symbol pins.
ERROR:sim:159 - An internal error has occurred. Closing SPI-4.2 Lite GUI.
Finished Generating.

Solution

There are a limited number of IP cores that do not generate an ASY file for schematic symbol generation. Most of these files are in the Communications & Networking category.

When a Core is created through Project Navigator, the CORE Generator Flow Vendor is set to ISE and an ASY file is expected to be produced. However, because no ASY file is available, the error above is generated.

To work around this error:
1. Open CORE Generator standalone or through the Project Navigator Manage Cores process.
2. Select the menu item Project -> Project Options.
3. Select the Generation tab of the project options and change the Vendor from ISE to Other.
4. Select other output files to generate as desired. NOTE: As the warning messages above indicate, many cores have a specific set of output file types.
5. If the IP Core was generated from CORE Generator standalone, the "<corename>.xco" file should now be added to the Project Navigator project using Project -> Add Source.

If you want a schematic symbol for the IP Core, create one using the following procedure:
1. Replace the ".xco" source with the HDL Functional Model of the core.
2. With the HDL Functional Model of the core selected, run the Create Schematic Symbol process under Design Utilities.
3. Replace the HDL Functional Model of the core with the ".xco" file in the Project Navigator sources.
AR# 22588
Date Created 09/04/2007
Last Updated 03/06/2008
Status Archive
Type General Article