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AR# 22589

LogiCORE PCI - Why does my Spartan-3E PCI design not work? Should Spartan-3E PCI Core designs use the PCILOGIC blocks? Why do I get hold violations when targeting a Spartan-3E?

Description

What are the PCILOGIC blocks?

Should Spartan-3E PCI designs use the special PCILOGIC blocks?

Why does my Spartan-3E design not appear to work?

Why do I get hold violations when targeting a Spartan-3E?

Solution

What are the PCILOGIC blocks?

The Spartan-3E device contains a special block of silicon called the PCILOGIC block. This block is used to assist in creating the output clock enable for the core and ensures OFFSET out or clock to out timing is met for this critical timing path. There are two of these special blocks of logic in the device. They are located on the right and left side of the device near the middle. This block is also contained in the Virtex, Virtex-E, Spartan-II, and Spartan-IIE devices.

Should Spartan-3E PCI designs use the special PCILOGIC blocks in the silicon?

PCI core designers using Step 0 Spartan-3E devices should not use the special PCILOGIC blocks. This block can be disabled by setting bit 251 in the core's configuration file to a 1. For more information, see (Xilinx Answer 10979) or the "Datapath Output Clock Enable" section in Chapter 3 of the PCI Core Getting Started User Guide.

This should not cause problems for 33 MHz designs, as there is enough slack in the 33 MHz OFFSET Out constraints to still meet timing. Xilinx has verified that 33 MHz PCI constraints can be met for the supported Spartan-3E designs without using the PCILOGIC blocks.

Why does my Spartan-3E design not appear to work?

Design downloaded to hardware may appear to be broken in Step 0 Spartan-3E devices if the PCILOGIC blocks are being used. This is due to a problem with the PCILOGIC blocks. Please disable the PCILOGIC blocks as directed above.

Why do I get hold violations when targeting a Spartan-3E?

If users do not set bit 251 in the configuration vector to a 1 to disable the special PCILOGIC block in the device, the timing tools will report hold violations. If you are using the v3.155 core, also ensure you have downloaded the updated UCF files for this build from (Xilinx Answer 22914).

AR# 22589
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article