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AR# 22606

MIG1.4 - Why is the first read/write operation assert for three clock cycles in Spartan-3 DDR design?


Key Words: Spartan-3, MIG, read, write, clock cycles

On a Spartan-3 DDR design from MIG1.4, the first read/write operation is asserted for three clock cycles, but the remaining address are asserted for only two clock cycles(BL=4). Why?


In Spartan-3 designs, to start with, you should assert the first address, command and data simultaneously and wait for the command acknowledge signal. The command ack assertion time will vary depending on the controller status. After the command acknowledge is asserted, you should wait for three clock cycles to pass the next address. This three-cycle time is "Active" to "Command" ( tRCD, Read or Write command) delay as per the memory specification. Subsequent addresses are passed once in two clock cycles, since the burst length supported was four.
AR# 22606
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article