Xilinx highly recommends avoiding complex loops in synthesis, as most synthesis tools have problems with this coding style. It is always best to write code that it is easy for the synthesis tool to utilize.
For more information on coding for synthesis, see the Synthesis and Simulation Design Guide accessible at:
http://www.xilinx.com/support/software_manuals.htmIf you must use loops, change the "for" loops to "while" loops because XST handles "while" loops better than "for" loops.
XST is working on addressing this issue in the future releases of software.